1. Field of the Invention
The present invention relates to a solid state image capturing apparatus and a camera apparatus having the same and, in particular, relates to those that convert analog signals that are output from unit pixels through column signal wires into digital signals and read the digital signals.
2. Description of the Related Art
In recent years, a column-parallel ADC equipped CMOS image sensor has been proposed. In this CMOS image sensor, analog-digital converters (hereinafter abbreviated as ADCs) are disposed correspondingly to columns of a matrix of unit pixels.
FIG. 1 is a block diagram showing a structure of a column-parallel ADC equipped CMOS image sensor 10 of the related art. In FIG. 1, a unit pixel 101 has a photodiode and an in-pixel amplifier. The pixels 101 are two-dimensionally arranged in a matrix shape and compose a pixel array section 102. Line control wires 103 (103-1, 103-2, and so forth) and column signal wires 104 (104-1, 104-2, and so forth) are, respectively, arranged for individual lines and individual columns of the matrix shaped pixel arrangement of the pixel array section 102. Line addresses and line scanning of the pixel array section 102 are controlled through the line control wires 103-1, 103-2, and so forth by a line scanning circuit 105.
ADCs 106 corresponding to the column signal wires 104-1, 104-2, and so forth are disposed on one end side of respective column signal wires and compose a column process section (column-parallel ADC block) 107. A digital-to-analog converter 108 that generates a ramp waveform reference voltage Vref for the ADCs 106 (hereinafter this converter is referred to as the DAC) is disposed. In addition, a counter 109 is disposed for the ADCs 106. The counter 109 counts in synchronization with a clock CK having a predetermined period and measures a time for a comparator 110 that will be described later to perform a comparison operation.
The ADC 106 has the comparator 110 that compares an analog signal, obtained from a unit pixel 101 of a selected line of the matrix through the column signal wire 104-1, 104-2, or the like, with a ramp waveform reference voltage Vref generated by the DAC 108. In addition, the ADC 106 has a memory 111 that stores a count value of the counter 109 based on a comparison output of the comparator 110 to provide a function of converting analog signals supplied from the unit pixels 101 into an N-bit digital signal.
The column addresses and column scanning of the ADCs 106 of the column process section 107 are performed by a column scanning circuit 112. In other words, N-bit digital signals that are digitally converted by the ADCs 106 are columnwise scanned by the column scanning circuit 112, read by a horizontal output wire 113 having an 2N-bit width, and sent to a signal process circuit 114 by a horizontal output wire 113. The signal process circuit 114 is composed of 2N sense circuits, 2N subtraction circuits, 2N output circuits, and so forth corresponding to the 2N-bit wide horizontal output wire 113.
A timing control circuit 115 generates clock signals and timing signals, with which the line scanning circuit 105, the ADCs 106, the DAC 108, the counter 109, the column scanning circuit 112, and so forth operate, based on a master clock MCK. The generated clock signals and timing signals are supplied to relevant circuit sections.
Next, the operation of the CMOS image sensor 10 shown in FIG. 1 will be outlined with reference to timing charts shown in FIG. 2A to FIG. 2C.
FIG. 2A shows a horizontal synchronous signal (H synchronization). FIG. 2B shows a clock supplied to the DAC 108, and the counter 109. FIG. 2C shows a ramp waveform reference voltage Vref that is output from the DAC 108.
The voltage of the ramp waveform changes as the clock occurs. The voltage of the ramp waveform and the output of a unit pixel are compared. The count value corresponding to the voltage of the unit pixel obtained by the comparison is stored in a memory 111. The count value stored in the memory 111 becomes a digital value of the unit pixel and is output.
FIG. 3A to FIG. 3F are timing charts showing an example of the more detailed operation of the CMOS image sensor 10.
With reference to FIG. 3A to FIG. 3F, after the first read operation from unit pixels 101 of a selected line to column signal wires 104-1, 104-2, and so forth has been established, a lamp waveform reference voltage Vref shown in FIG. 3A is supplied from the DAC 108 to the comparators 110. Thus, the comparators 110 compare the signal voltages Vx of the column signal wires 104-1, 104-2, and so forth with the reference voltage Vref. In this comparison operation, when the reference Vx becomes the same as the signal voltage Vx, the polarity of the output of the comparator 110 is inverted. When the output of the comparator 110 is inverted, the memory 111 stores a count value N1 of the counter 109 corresponding to a comparison time of the comparator 110. FIG. 3C shows a clock that generates a count value. FIG. 3D shows changes of the count value N.
In the first read operation, as shown in FIG. 3E, a reset component ΔV of each unit pixel 101 is read. The reset component Δ contains as an offset a fixed pattern noise that varies between unit pixels 101. However, the fluctuation of the reset component is generally small and the reset level is common in all pixels. Thus, in the first read operation, the signal voltage Vx of each of the column signal wires is nearly known. Consequently, when the reset component ΔV is read in the first read operation, by adjusting the ramp waveform reference voltage Vref, the comparison time of the comparator 110 can be relatively shortened.
In the second read operation, in addition to the reset component ΔV, a signal component corresponding to the amount of incident light of each of the unit pixels 101 is read in the same manner as the first read operation. In other words, after the second read operation from unit pixels 101 of the selected line to the column signal wires 104-1, 104-2, and so forth has been established, the ramp waveform reference voltage Vref is supplied from the DAC 108 to the comparator 110. Thus, the comparators 110 compare the signal voltage Vx of the column signal wires 104-1, 104-2, and so forth with the reference voltage Vref.
When the reference voltage Vref is supplied to the comparators 110, the counter 109 performs a second counting operation. In the second counting operation, when the reference voltage Vref becomes the same as the reference voltage Vx, the polarity of the output of the comparator 110 is inverted. When the output of the polarity is inverted, as shown in FIG. 3F, the memory 111 stores a count value N2 of the counter 109 corresponding to a comparison time of the comparator 110. At this point, the first count value N1 and the second count value N2 are stored in different locations of the memory 111.
After the foregoing sequence of the AD conversion operations has been complete, the column scanning circuit 112 scans respective columns. As a result, the first and second N bit digital signals stored in the memory 111 are supplied to the signal process circuit 114 through the 2N-bit wide horizontal output wire 113. A subtraction circuit (not shown) of the signal process circuit 114 performs a subtraction process of (second operation signal)−(first operation signal). Thereafter, the resultant signal is output to the outside of the CMOS image sensor 10. Thereafter, the same operation is repeated for each line and thereby a two-dimensional image is generated.
Japanese Unexamined Patent Application Publication No. 2005-278135, hereinafter referred to as Patent Document 1, describes an example of a solid state image capturing apparatus shown in FIG. 1.